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职位名称 职位类型 工作地点 操作
Job Description
As part of the SoC design team, engineer will mainly focus on following areas, but not limited to:
-Prepare micro-architecture specification for IP, subsystem or chip;
-RTL implementation and perform integration into SOCs.
-3rd party IP configuration , optimization
-Subsystem design with in-house design and 3rd party IP
-Subsystem implementation, including synthesis/linting/cdc/DCG flow/…
-Assist with backend team on perform place-and-route and timing analysis of modules
-Assist with chip bring up and perform silicon functional/performance validation.

Job Requirement
- M.Sc. or Ph.D. degree in electrical engineering, computer engineering or equal
- Good background in C, Verilog, SystemVerilog and verification methodology.
- A high-level of self-motivation and a proactive approach to solving problems
Job Description
As part of the SoC design team, engineer will mainly focus on following areas, but not limited to:
-Prepare micro-architecture specification for IP, subsystem or chip;
-RTL implementation and perform integration into SOCs.
-3rd party IP configuration , optimization
-Subsystem design with in-house design and 3rd party IP
-Subsystem implementation, including synthesis/linting/cdc/DCG flow/…
-Assist with backend team on perform place-and-route and timing analysis of modules
-Assist with chip bring up and perform silicon functional/performance validation.

Job Requirement
- M.Sc. or Ph.D. degree in electrical engineering, computer engineering or equal
- Good background in C, Verilog, SystemVerilog and verification methodology.
- A high-level of self-motivation and a proactive approach to solving problems
Job Description
As part of the SoC design team, engineer will mainly focus on following areas, but not limited to:
-Prepare micro-architecture specification for IP, subsystem or chip;
-RTL implementation and perform integration into SOCs.
-3rd party IP configuration , optimization
-Subsystem design with in-house design and 3rd party IP
-Subsystem implementation, including synthesis/linting/cdc/DCG flow/…
-Assist with backend team on perform place-and-route and timing analysis of modules
-Assist with chip bring up and perform silicon functional/performance validation.

Job Requirement
- M.Sc. or Ph.D. degree in electrical engineering, computer engineering or equal
- Good background in C, Verilog, SystemVerilog and verification methodology.
- A high-level of self-motivation and a proactive approach to solving problems
ob Description

1. Responsible for Front-End implementation work from RTL2Netlist, including SDC/UPF/Synthesis/STA/FM/Lint/CDC. (Professional Direction)
1. 负责ASIC前端设计实现工作(RTL -> 网表),包括:时序&功耗约束/综合设计/时序分析/形式验证/RTL语法&跨时钟域检查。 (专家方向)

2. Responsible for DFT work, including Lbist/Mbist/Scan/ATPG/Boundary Scan design & simulation.
2. 负责DFT相关的工作,包括:上电自测试/memory 测试/SCAN 测试/边界测试的设计以及仿真工作。

3. Responsible for ASIC design flow development & optimization.
3. 负责搭建ASIC 设计实现/DFT的flow,以及优化。

4. Closely co-work timing & power closure with P&R.
4. 和后端一起合作,实现时序和功耗的收敛。


Job Requirement
1. Understand ASIC design flow. Basic knowledge including Synthesis/STA/FM/CDC is a plus.
1. 了解ASIC设计流程。如果了解“综合/时序分析/形式验证/跨时钟域设计”中的其中一项是加分项。

2. Basic knowledge including LEC/SDC/UPF/DFT is a plus.
2. 如果了解“时序约束/功耗约束/DFT设计”中的其中一项是加分项。

3. Familiar with unix/linux and scripts (python, tcl, perl, makefile etc.) is a plus.
3. 熟悉“unix/linux,Python/TCL/Perl/Makefile”中的其中一项是加分项。

4. Familiar with front-end EDA tools and flows is a plus.
4. 熟悉前端EDA设计工具是加分项。

5. A high-level of self-motivation and a proactive approach to solving problems.
5. 高度的自我激励和主动解决问题的意愿。
ob Description

1. Responsible for Front-End implementation work from RTL2Netlist, including SDC/UPF/Synthesis/STA/FM/Lint/CDC. (Professional Direction)
1. 负责ASIC前端设计实现工作(RTL -> 网表),包括:时序&功耗约束/综合设计/时序分析/形式验证/RTL语法&跨时钟域检查。 (专家方向)

2. Responsible for DFT work, including Lbist/Mbist/Scan/ATPG/Boundary Scan design & simulation.
2. 负责DFT相关的工作,包括:上电自测试/memory 测试/SCAN 测试/边界测试的设计以及仿真工作。

3. Responsible for ASIC design flow development & optimization.
3. 负责搭建ASIC 设计实现/DFT的flow,以及优化。

4. Closely co-work timing & power closure with P&R.
4. 和后端一起合作,实现时序和功耗的收敛。


Job Requirement
1. Understand ASIC design flow. Basic knowledge including Synthesis/STA/FM/CDC is a plus.
1. 了解ASIC设计流程。如果了解“综合/时序分析/形式验证/跨时钟域设计”中的其中一项是加分项。

2. Basic knowledge including LEC/SDC/UPF/DFT is a plus.
2. 如果了解“时序约束/功耗约束/DFT设计”中的其中一项是加分项。

3. Familiar with unix/linux and scripts (python, tcl, perl, makefile etc.) is a plus.
3. 熟悉“unix/linux,Python/TCL/Perl/Makefile”中的其中一项是加分项。

4. Familiar with front-end EDA tools and flows is a plus.
4. 熟悉前端EDA设计工具是加分项。

5. A high-level of self-motivation and a proactive approach to solving problems.
5. 高度的自我激励和主动解决问题的意愿。
ob Description

1. Responsible for Front-End implementation work from RTL2Netlist, including SDC/UPF/Synthesis/STA/FM/Lint/CDC. (Professional Direction)
1. 负责ASIC前端设计实现工作(RTL -> 网表),包括:时序&功耗约束/综合设计/时序分析/形式验证/RTL语法&跨时钟域检查。 (专家方向)

2. Responsible for DFT work, including Lbist/Mbist/Scan/ATPG/Boundary Scan design & simulation.
2. 负责DFT相关的工作,包括:上电自测试/memory 测试/SCAN 测试/边界测试的设计以及仿真工作。

3. Responsible for ASIC design flow development & optimization.
3. 负责搭建ASIC 设计实现/DFT的flow,以及优化。

4. Closely co-work timing & power closure with P&R.
4. 和后端一起合作,实现时序和功耗的收敛。


Job Requirement
1. Understand ASIC design flow. Basic knowledge including Synthesis/STA/FM/CDC is a plus.
1. 了解ASIC设计流程。如果了解“综合/时序分析/形式验证/跨时钟域设计”中的其中一项是加分项。

2. Basic knowledge including LEC/SDC/UPF/DFT is a plus.
2. 如果了解“时序约束/功耗约束/DFT设计”中的其中一项是加分项。

3. Familiar with unix/linux and scripts (python, tcl, perl, makefile etc.) is a plus.
3. 熟悉“unix/linux,Python/TCL/Perl/Makefile”中的其中一项是加分项。

4. Familiar with front-end EDA tools and flows is a plus.
4. 熟悉前端EDA设计工具是加分项。

5. A high-level of self-motivation and a proactive approach to solving problems.
5. 高度的自我激励和主动解决问题的意愿。
ob Description
As part of the SoC design team, engineer will mainly focus on following areas, but not limited to:
-Prepare micro-architecture specification for IP, subsystem or chip;
-RTL implementation and perform integration into SOCs.
-3rd party IP configuration , optimization
-Subsystem design with in-house design and 3rd party IP
-Subsystem implementation, including synthesis/linting/cdc/DCG flow/…
-Assist with backend team on perform place-and-route and timing analysis of modules
-Assist with chip bring up and perform silicon functional/performance validation.

Job Requirement
- M.Sc. or Ph.D. degree in electrical engineering, computer engineering or equal
- Good background in C, Verilog, SystemVerilog and verification methodology.
- A high-level of self-motivation and a proactive approach to solving problems
ob Description
As part of the SoC design team, engineer will mainly focus on following areas, but not limited to:
-Prepare micro-architecture specification for IP, subsystem or chip;
-RTL implementation and perform integration into SOCs.
-3rd party IP configuration , optimization
-Subsystem design with in-house design and 3rd party IP
-Subsystem implementation, including synthesis/linting/cdc/DCG flow/…
-Assist with backend team on perform place-and-route and timing analysis of modules
-Assist with chip bring up and perform silicon functional/performance validation.

Job Requirement
- M.Sc. or Ph.D. degree in electrical engineering, computer engineering or equal
- Good background in C, Verilog, SystemVerilog and verification methodology.
- A high-level of self-motivation and a proactive approach to solving problems
ob Description
As part of the SoC design team, engineer will mainly focus on following areas, but not limited to:
-Prepare micro-architecture specification for IP, subsystem or chip;
-RTL implementation and perform integration into SOCs.
-3rd party IP configuration , optimization
-Subsystem design with in-house design and 3rd party IP
-Subsystem implementation, including synthesis/linting/cdc/DCG flow/…
-Assist with backend team on perform place-and-route and timing analysis of modules
-Assist with chip bring up and perform silicon functional/performance validation.

Job Requirement
- M.Sc. or Ph.D. degree in electrical engineering, computer engineering or equal
- Good background in C, Verilog, SystemVerilog and verification methodology.
- A high-level of self-motivation and a proactive approach to solving problems

Job Description:

Lead or co-lead the team to achieve verification target of state-of-the-art ARM based SoC, or one of its sub-system. Be responsible for verification quality and schedule.

1、Lead the verification process, decompose tasks for each team member.

2、Create verifcation plan and review with architecture/design team.

3、Create random constraint test bench based on the requirement.

4、Create random test cases and direct test cases to achieve coverage goals.

5、Work closely with architecture/design team to identify problems.

6、Low-power verification.

7、Performance verification.

8、Finish verification tasks on time.

  1. Job Requirements:

1、 Bachelor or above with more than 5 years’ work experience.

2、 Proficient with System Verilog & UVM.

3、 Expert in the use of Cadence/Synopsys verification tools.

4、 Verification experience on automotive chip is a great plus.

5、 CPU/GPU/ISP/DDR architecture knowledge is a great plus.

6、 high speed interface protocol knowledge is a great plus: PCIe/USB3.1/Ethernet, etc.

verification experience using Palladium/ZeBU is a great plus.

scripting languages (Python, Perl, Makefile, …) is an additional plus.

C and ARMv8.x assembly code programming skill is an additional plus.

Good communication skills.

JobDescription   

As a member of thePD team, you will build the next generation IVI, ADAS SoC in advanced process.

You will drive thebackend flow through the entire NETLIST 2 GDS process including floorplanning,P&R, STA, PV and PI . You will also conduct PPA optimization.

 

Yourresponsibilities include, but not limited to:

- Build backend flowon state-of-the-art processing node

- Create SPECs forPD sign-off

- Work closely witharchitecture and design team to optimize PPA

- Floor planning,equivalence checks, partitioning, IO assignment and IP integration, CTS andpower grid, P&R , timing closure, power analysis etc.

- function andtiming ECOs and sign-offs

 

JobRequirements  

- BS majoring inCS/EE, MSEE is preferred.

- Courses taken incomputing science, digital design, circuit design, device modeling or related.

- Knowledge ofdevice model, processing technology, timing, noise and power in chip design isprefered.

- Knowledge ofpython/perl/tcl, and good programming ability. Debug experience is preferred.

- Experience onphysical design implementation(any of: floorplan, Place & Route, STA,LVS/DRC) or ASIC design is preferred.

- Hand-on experiencein EDA software from Synopsys (PC/ICC/DC/PT/STAR-RC), Cadence (Innovus/Voltus)is preferred.

JobDescription   

As a member of thePD team, you will build the next generation IVI, ADAS SoC in advanced process.

You will drive thebackend flow through the entire NETLIST 2 GDS process including floorplanning,P&R, STA, PV and PI . You will also conduct PPA optimization.

 

Yourresponsibilities include, but not limited to:

- Build backend flowon state-of-the-art processing node

- Create SPECs forPD sign-off

- Work closely witharchitecture and design team to optimize PPA

- Floor planning,equivalence checks, partitioning, IO assignment and IP integration, CTS andpower grid, P&R , timing closure, power analysis etc.

- function andtiming ECOs and sign-offs

 

JobRequirements  

- BS majoring inCS/EE, MSEE is preferred.

- Courses taken incomputing science, digital design, circuit design, device modeling or related.

- Knowledge ofdevice model, processing technology, timing, noise and power in chip design isprefered.

- Knowledge ofpython/perl/tcl, and good programming ability. Debug experience is preferred.

- Experience onphysical design implementation(any of: floorplan, Place & Route, STA,LVS/DRC) or ASIC design is preferred.

- Hand-on experiencein EDA software from Synopsys (PC/ICC/DC/PT/STAR-RC), Cadence (Innovus/Voltus)is preferred.

JobDescription   

As a member of thePD team, you will build the next generation IVI, ADAS SoC in advanced process.

You will drive thebackend flow through the entire NETLIST 2 GDS process including floorplanning,P&R, STA, PV and PI . You will also conduct PPA optimization.

 

Yourresponsibilities include, but not limited to:

- Build backend flowon state-of-the-art processing node

- Create SPECs forPD sign-off

- Work closely witharchitecture and design team to optimize PPA

- Floor planning,equivalence checks, partitioning, IO assignment and IP integration, CTS andpower grid, P&R , timing closure, power analysis etc.

- function andtiming ECOs and sign-offs

 

JobRequirements  

- BS majoring inCS/EE, MSEE is preferred.

- Courses taken incomputing science, digital design, circuit design, device modeling or related.

- Knowledge ofdevice model, processing technology, timing, noise and power in chip design isprefered.

- Knowledge ofpython/perl/tcl, and good programming ability. Debug experience is preferred.

- Experience onphysical design implementation(any of: floorplan, Place & Route, STA,LVS/DRC) or ASIC design is preferred.

- Hand-on experiencein EDA software from Synopsys (PC/ICC/DC/PT/STAR-RC), Cadence (Innovus/Voltus)is preferred.

SUMMARY:

The primary objective of this role is to manage the programs/projects, focusing on the program/project planning and execution per the scope, time, and budget.


MAIN RESPONSIBILITIES:

1. Formulates the overall Program/Project Management plan, in consultation with management and other parties concerned, and based on the engineering team’s and functional lead engineers’ input.

2. Specifies the program/project scope and quality standard, schedule, phases/milestones, resource requirements, overall cost/budget, risk assessment, and risk mitigation plan.

3. Executes and keeps updated the Program/Project Management Plan, clearly indicating program/project deliverables and quality, phase gates and milestones, resource and cost/budget, and risk assessment/mitigation.

4. Organizes the expert reviews and peer reviews to ensure program/project plan quality; organizes periodical program/project reviews, including phase gate reviews and milestone reviews; reports periodically the program/project status, progress, key issues and corresponding solutions.

5. Ensures effective transfer and archiving of the program/project results, documents, and the associated knowledge base.

6. Organizes lessons learned sessions after big milestones or phase gates, for continuous improvement.

7. Owns the entire end-to-end program/project planning and execution from cradle to volume production, by leveraging the cross-functional teams in the entire organization.

8. Owns the program/project execution metrics; escalates via exception report when project scope/quality, schedule, cost targets or budget/resources deviation out of the pre-defined boundary; follows up and leads the execution of the mitigation plan after the exception review.

9. Assistant the change management process from program/project start until volume production

10. Assistant the product management including NPI, product launch and lifecycle management

11. Participates in and contributes to the program/project flow, processes, methodology, and infrastructure set-up, including program/project management tools.

12. Takes other tasks assigned.


KEY RELATIONS AND INTERFACES:

1. Internal – Program Management, promote collaboration, cross-functional Teams such as Engineering, Operations, and other Support team.

2. External – Partners, sub-contractors, license administration bodies, certification bodies, and key customers.


REQUIREMENTS:

1. Education and Qualification:

B.S. degree in Computer Science, Engineering or related field, Master degree highly preferred.

PMP certification highly preferred.

2. Working Experience:

5+ years in engineering/R&D, project management and program management; product management experience a plus.

Experience in program/project flow, processes, methodology, and infrastructure set-up highly preferred.

Multi-national company working experience in semiconductor industry and/or Software & System industry preferred.

3. Technical and Professional Knowledge:

Extensive experience in the program/project management in semiconductor and/or software & system industry.

Deep understanding of IC technology and related software & system, experience in the SoC design and relevant applications is a plus.

Strong communication ability, written and verbal, with multi-levels of internal and external interfaces.

Strong program/project management skills and practices; fluent in project management tools.

Documentation skills, fluent in MS Office (Word, Excel, PowerPoint, SharePoint, etc.).

4. Natural Talents (Innate Competencies/Behaviors):

High sense of ownership and accountability

High sense of leadership and influence

Ability to manage conflicts

Organized, detail-oriented, and pursuit of excellence

Eager to make an impact

Eager to make continuous improvement

Reactivity and self-initiative

Customer-friendly

岗位职责:

1.     与职能部门密切合作,从协助解决问题的角度向职能部门提供法务支持,帮助职能部门在法律框架内实现其业务目标;

2.     起草、审查各类商业合同并在需要时参与/协助谈判;

3.     准备并提供法务相关培训(新员工入职培训和其他需要的具体培训);

4.     协助管理知识产权相关事宜,包括但不限于专利、商标等;

5.     按需求开展法律研究并提供相关法律咨询服务和指导;

6.     履行法务部门负责人指派的其他职责。

岗位要求:

1.     本科以上学历,法律专业;

2.     五年以上法律工作经验,有研发公司工作经验并曾参与过公司上市项目的尤佳;

3.     有独立审核和修改英文合同的能力;

4.     工作中高度关注细节,在能力范围内力求做到更好;

5.     具有同时协调多个项目/任务并准确及时完成任务的能力;

6.     具有良好的团队合作精神。